1. Field of the Invention
The invention generally relates to memory management in computing systems and more specifically relates to methods and structures for bypassing complexity associated with memory management features of typical memory management coprocessors. The invention is particularly useful in embedded system applications where the complexity of feature-rich memory management for virtual addressing is unnecessary.
2. Discussion of Related Art
Computing systems generally comprise one or more general and/or special purpose processors coupled to one or more types of memory devices. The memory devices are generally utilized for storing program instructions to be executed by the various processors of the system and for storing data to be manipulated by the operating program instructions. Most present-day computing systems include one or more hierarchical layers of memory for such purposes. First, a main memory structure provides the desired capacity of memory required for storage of executing programmed instructions and/or associated data. The main memory may consist of any combination of volatile and nonvolatile memory including both random access memory (RAM) and read only memory (ROM). One or more additional hierarchical layers of memory may be designated as cache memory. The cache memory typically is higher performance memory relative to the devices selected for the main memory structure. Given the higher performance and associated higher cost, cache memory is generally smaller in capacity as compared to the main memory structure.
In particular, as regards the main memory structure, many computing applications require substantially more capacity for stored program instructions and associated data than may be practically achieved with semiconductor, electronic memory devices. For this reason, methods and structures associated with virtual memory where a secondary or backing store such as a disk drive is used to provide an essentially unlimited extension to the size of the main memory. When particular portions of program instructions or related data are required, virtual memory management features determine whether the requested instructions or data are presently residing in main memory (or in higher speed cache memory) if the requested information is available, it is returned from the main memory or cache memory structure in which it was found to the requesting processor. If the requested information is not present in the main memory or cache memory structures, the virtual memory management features retrieve the information from the backing store (i.e. from a disk drive) and restore the retrieved information in an appropriate location of main memory (and/or cache). Numerous other mapping and security features are typically included with such virtual memory management features of a system.
As presently practiced in the art, a number of memory management related features are typically integrated within a single memory management coprocessor—a portion of the supporting “chip set” associated with a particular processor architecture. For example, typical memory management coprocessors include logic to control low level interaction with memory devices, virtual memory management features, and cache memory management features. In some memory management, processors, these features may be co-resident and continuously operable such that the system designer must provide appropriate supporting circuits and memory to enable proper functioning of each of these features embedded within the memory management coprocessor.
In many computing applications such as personal computers and workstations, all of these memory management features are typically applied to operation of the computing system. However, in a number of computing applications such as embedded computing applications, some of these features may be unnecessary or even a hindrance to the overall architecture. In particular, in embedded systems such as a storage controller computing application, it may be a problem to utilize such a complex memory management coprocessor. In many such embedded computing applications, particular memory management features are not required and may add complexity and/or related cost to the embedded application. For example, a typical embedded computing application may properly utilize the low level memory device interface features of a memory controller and the cache memory management features of a memory controller but would typically have little or no need for the virtual memory management and mapping features of most memory controllers. The virtual memory features of a typical memory management coprocessor often requires the addition of a memory component for storing translation table information associated with virtual memory address translation.
Although such virtual memory management and mapping features are less useful in such embedded computing applications, as presently practiced in the art, the embedded systems designer must none the less provide associated supporting circuitry and memory dedicated to the translation tables typically required by virtual memory management features. Providing this extra control circuitry and associated memory can add significant cost and complexity to an embedded system computing application.
It is evident from the above discussion that a need exists for improved structures and methods to reduce the need for wasteful complexity and/or cost associated with memory controllers and memory management in simpler, computing applications such as embedded computing applications.